In NAND flash memories, data is written to one page which is activated by one word line. Therefore, memory cells existing in one same page need be subjected simultaneously to writing and non-writing at the same time.
Conventional NAND flash memories employ a self-boost operation to perform a non-write operation. In the self-boost operation, an internal power supply potential (VDD) is transferred to channels of NAND strings, to inhibit writing to non-selected memory cells. Thereafter, selected gate transistors are turned off, to put the NAND strings internally into a floating state. Thereafter, selected and non-selected word lines are respectively increased to predetermined potentials, and accordingly, channel potentials of the NAND strings increase due to coupling. Therefore, a potential difference between control gates applied with a writing voltage (also named a program voltage) and channels is decreased to be put in non-writing.
A potential of a floating gate is determined by a potential of a channel, a potential of a control gate, and capacity coupling with adjacent floating gates. For a written cell, the potential of the channel is set to a ground potential VSS by a bit line. For a unwritten cell, the potential of the channel is set to a boost potential, an initial potential of which is the VDD supplied from a bit line as described above.
In a product which employs all bit lines (ABL), all memory cells selected by one word line are simultaneously made accessible. That is, when writing data, all memory cells selected by one word line are simultaneously subjected to writing, on NAND strings connected to even-numbered bit lines and odd-numbered bit lines.
NAND flash memories also perform step-up writing in which a program voltage is gradually stepped up in order to increase writing efficiency and further to accurately control a width of a threshold voltage distribution (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-23044). In the step-up writing, if writing for the first time does not pass, the writing is tried again with a program voltage increased by a constant voltage (corresponding to a step-up voltage). This writing loop is repeated to set a target threshold voltage in memory cells. When the step-up writing is applied to the ABL technique, a problem takes place as follows.
Unwritten cells are maintained in an unwritten state from the begging to the end of a writing loop. In contrast, written cells are set in a written biased state in the beginning of the writing loop. As writing progresses, writing passes in the writing loop for the (N−1)-th time. In this case, in the writing loop for the N-th time, the written cells are set in an unwritten biased state. According to the ABL technique, writing is performed on both odd-numbered and even-numbered bit lines. Therefore, a biased state of a floating gate adjacent to a memory cell (M1) being subjected to writing differs between in writing for the (N−1)-th time and in writing for the N-th time. That is, in writing for the N-th time, a potential of a floating gate of a memory cell of interest differs between when writing to an adjacent memory cell passes and when the writing to the adjacent memory cell does not passed. Specifically, when the writing does not pass, a channel for the adjacent cell is set to VSS. When the writing passes, the channel is set to a boost potential which is the VDD as an initial potential. Therefore, a potential of a floating gate of a memory cell for which writing to an adjacent memory cell passes is increased by capacitive coupling.
Accordingly, at the time when writing to an adjacent memory cell passes, the potential of the floating gate of the adjacent memory cell increases. The potential of the floating gate of the memory cell of interest also increases under influence of capacitive coupling. Therefore, a greater writing voltage than a voltage by which a program voltage is stepped up under control of a control gate is supplied. As a result, the memory cell of interest causes excessive writing (over-programming).
Hence, there is a demand for a non-volatile semiconductor memory device capable of preventing over-programming when writing is performed on all memory cells selected by one word line.